This invention relates to memory and logic circuits using a high speed semiconductor device, and more particularly to applications of a controlled avalanche triode in a memory device, a switch device, and in various logic devices and circuits.
It is desirable in the semiconductor industry to have memory and logic devices with the following attributes: made of silicon so that the device can be incorporated into present LSI (large scale integration) technology, simple to fabricate, simple to operate, small size as to per unit memory or unit logic step so as to be practical in LSI circuitry, fast with a switching time of less than 1 nanosecond, small power consumption with a power-delay time product of less than 10.sup.-12 joules, simple cascading topology for easy access and transfer of logic data, and nonvolatile. With the exception that the high speed avalanche memory triode herein described is a volatile device, all of these criteria and characteristics are satisfied.
Although there are many different types of volatile memory and logic devices, several can be mentioned by way of comparing their relative merits. The Josephson junction flip-flop "and" logic gate disclosed in the literature in 1975 is fast with low power dissipation and a small power-delay time product by the above criteria, but these are superconductive elements and do not have general applications since the circuit must be cryogenized. Schottky gate Gunn logic devices are as fast with a comparable power-delay time product; however, the device employs unique properties of gallium arsenide and, hence, is not amemable to silicon LSI technology. Further, such a device has large power density consumption requirements and is not suitable for continuous wave applications. State-of-the-art silicon logic devices, such as diodes, transistors, and I.sup.2 L (Integrated Injection Logic) devices, basically use a minimum cell of at least two active devices connected as a flip-flop, although I.sup.2 L devices take advantage of better interconnection topology. The delay time is long, typically 10 nanoseconds per gate, while the power consumption is low with a comparable power-delay time product by the above criteria. The present invention in particular is an improvement over such silicon logic devices.